Turning to FIG. 1, an example of a conventional system 100 can be seen. In this system 100, hosts 102-1 to 102-N (which can be; for example, a computer, router, or switch) are able to communicate with one another over communications medium 112 (which can; for example, be an optical fiber, backplane, or twisted pair) through network interfaces 104-1 to 104-N. In this example, the network interfaces 104-1 to 104-N employ Ethernet over Electrical Backplanes and, more specifically, 10 GBase-KR. A description of 10 GBase-KR can be found in the Institute of Electrical and Electronics Engineers (IEEE) standard 802.3-2008 (which is dated Dec. 26, 2008 and which is incorporated by reference herein for all purposes). These network interfaces 104-1 to 104-N employ media access control (MAC) circuits 106-1 to 106-N that communicate with PHYs 110-1 to 110-N, via media independent interfaces (MIIs) 108-1 to 108-N (which can typically have half-duplex or full-duplex operation), each of which is described in IEEE standard 802.3-2008.
Of interest here, however, are PHYs 110-1 to 110-N, and, as can be seen in greater detail in FIG. 2, PHYs 110-1 to 110-N (hereinafter PHY 110), PHY 110 employs several sublayers. This PHY 110 can be an independent integrated circuit (IC) or can be integrated with a MAC circuit (i.e., MAC circuit 106-1) and an MII 108. As shown, the PHY 110 is generally comprised of physical medium dependent (PMD) sublayer logic 212; physical medium attachment (PMA) sublayer logic 210, forward error correction (FEC) sublayer logic 204, and physical coding (PCS) sublayer logic 202. These sublayer logic circuits 202, 204, 210, and 212 interact with one another to provide communications between MII 108 and communications medium 112. For transmission, the FEC sublayer logic 204 employs an encoder 206 as described in IEEE standard 802.3-2008, clause 74, and, for reception, the FEC sublayer logic 204 employs a decoder 308 as described in IEEE standard 802.3-2008, clause 74.
As can be seen in FIG. 3, the PCS sublayer logic 202 can be a transceiver, having a PCS transmitter 302 and a PCS receiver 304. The transmitter 302, in this example, is able to receive data from MII 108, encode the data with encoder 306, scramble the encoded data with scrambler 308, and convert (so as to be used by FEC sublayer logic 204) with gearbox 310. The receiver 304, in this example, is able to convert data from FEC sublayer logic 204 using gearbox 312, descramble the data with descrambler 314, and decode the data (for use with MII 108) with decoder 316. The details of PCS sublayer logic 202 can, for example, be seen in IEEE standard 802.3-2008, clauses 48 and 74.
Of interest here are the scrambler 308 and descrambler 314. In this example, the scrambler 308 and descrambler 314 are able to perform data scrambling/descrambling and error checking. One purpose in scrambling/descrambling data with the PHYs 110-1 to 110-N is to substantially randomize the data to reduce the impact of electromagnetic interference (EMI) and improve signal integrity. This is typically accomplished by the use of a pseudorandom bit sequence (PRBS) generated with a specified polynomial. For example, for 8b/10b encoding, a PRBS-7 (or 1+x6+x7) can be employed, and, for synchronous optical networking or SONET (as specified in ITU O.150), PRBS-23 (or X23+X18+1). Similarly, this PRBS signaling can be employed for error checking.
However, as demonstrated above, one polynomial is generally not applicable to all standards (e.g., 802.3-2008 and SONET); each standard usually specifies its own polynomial. Conventionally, this meant that each PHY (e.g., 110-1) would be designed for a particular standard (e.g., PRBS-7 for 802.3-2008) and would lack the flexibility to be used with other standards. A reason for this is that the serial and parallel implementations for the PHYs (e.g., 110-1) would be too costly in terms of area, price, and power consumption to be generally applicable.
Therefore, there is a need for a flexible transceiver architecture.
Some examples of conventional systems are: U.S. Pat. No. 4,744,104; U.S. Pat. No. 5,267,316; U.S. Pat. No. 6,820,230; U.S. Pat. No. 6,907,062; U.S. Pat. No. 7,124,158; U.S. Pat. No. 7,414,112; U.S. Pat. No. 7,486,725; U.S. Pat. No. 7,505,589; U.S. Patent Pre-Grant Publ. No. 2003/0014451; U.S. Patent Pre-Grant Publ. No. 2007/008997; and U.S. Patent Pre-Grant Publ. No. 2007/0098160.